Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) chip comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a transistor for opening and closing charge and discharge passages of the capacitor. The number of bits on DRAM chips has been increasing by approximately 4.times. every three years; this increase has been achieved through improvements in photolithographic techniques used to fabricate chips and innovations in cell design.
Among the first of these innovations was the use of three dimensional cell structures that utilized area above the silicon surface (stacked capacitor) or below the silicon surface (trench capacitor) for the storage capacitor. Since their introduction with the 4 M generation, trench capacitor innovations have kept pace with lithographic improvements. This has been accomplished largely by making structural changes inside the storage trench.
However, 64 M DRAM contained little cell structure innovation, hence DRAM cell size has not decreased in the same historical rate from the preceding 16 M generation. This has led to a larger chip and lower productivity of the 64 M DRAM cell than was predicted. The same trend is extending out through 256 M. In order to achieve acceptable cell size, new structures must be developed which require only 4 lithographic squares compared to current 8 square cells.